From vikas at vikaskumar.org  Mon Jul  7 10:27:50 2014
From: vikas at vikaskumar.org (Vikas N Kumar)
Date: Mon, 07 Jul 2014 13:27:50 -0400
Subject: [Hardware-pm] Module::Build::Xilinx 0.01 released
In-Reply-To: <53B38623.9040600@cpan.org>
References: <53B38623.9040600@cpan.org>
Message-ID: <53BAD896.605@vikaskumar.org>

Hi

Module::Build::Xilinx 0.04 has been released now.

This actually gives a more perl-ish feel to the Xilinx ISE workflow.
Instead of the user having to use Xilinx's Tcl executable to run the Tcl
script generated, the Module::Build::Xilinx has actions that manage that
instead and keeps it clean for the user.

So the user has to do just something like the following to, say, create
the project for Xilinx ISE:

$ ./Build psetup

and it will do the rest.

Similarly for building the project and running a testbench

$ ./Build pbuild
$ ./Build test

for viewing the output of the testbench using Xilinx's ISimGui

$ ./Build view

For programming the bitstream to a device:

$ ./Build program --device=/dev/my_device

I have tried to make it as clean as possible.

It works well on Windows and Linux 32 and 64-bit systems.

Hope someone finds this useful to get started with or improve their FPGA
development workflow by using Perl instead of Tcl.

Thanks
Vikas.

On 07/02/2014 12:10 AM, Vikas N Kumar wrote:
> Hi
>
> For those of you who are into learning FPGA development using developer
> boards made by Xilinx such as the Spartan-3A Starter Kit, I have
> released Module::Build::Xilinx into CPAN right now.
>
> The aim of this module is to enable you to create a custom Tcl makefile 
> like program for your VHDL project for the Xilinx dev board, so that you
> can actually completely use command line to setup, build, run , simulate
> and even program your Xilinx device by running the generated Tcl
> makefile with Xilinx's custom Tcl shell.
>
> This module enables you to write a much simpler Build.PL script with
> some special parameters that will help auto-generate a complex Tcl file
> to make it easier to use Xilinx's ISE WebPack IDE from the commandline.
>
> Currently as of version 0.01 it only supports VHDL and if any Verilog
> users are interested I can support that too.
>
> For an example, look in the share/example directory of the source code
> or in the share/ directory of the installation to see how to use it with
> VHDL source and test files.
>
> Feel free to email me on further details.
>
> Thanks
> vicash (vikas at cpan.org)
>