[boulder.pm] Perl Reference Problems (with a hint of verilog)

Jeff Pream jpream at maxtor.com
Tue Apr 9 17:16:16 CDT 2002


Sorry about the word wrap..  If you'd like a non-wrapped version let me
know and I'll repost.

Jeff Pream wrote:

> A little back ground..  I have taken a verilog netlist and created a
> data structure (hash of hashes..) to allow me to easily check certain
> constructs within the netlist.  The data structure looks something like
> this:
>
> $pointer->{$module}{"sub_mod"}{$submodule}{$inst}{$port} =
> $connected_wire;
> $pointer->{$module}{"clocks"}{$clock} = $arbitrary_number; #just need
> the name
> $pointer->{$module}{"port"}{"in"}{$port_name} = $arbitrary_number; #just
> need the name
> $pointer->{$module}{"port"}{"out"}{$port_name} = $arbitrary_number;
> #just need the name
> $pointer->{$module}{"port"}{"inout"}{$port_name} = $arbitrary_number;
> #just need the name
> $pointer->{$module}{"port"}{"unknown"}{$port_name} = $arbitrary_number;
> #module not declared
> @{$pointer->{$module}{"wire"}} = @wire_list_of_module;
> $pointer->{$module}{"used_by"}{$parent_module}{$inst_name}{$clk_port} =
> $connected_wire; #added after initial data struct built
> $pointer->{$module}{"declared"} = $arbitrary_number; #module is locally
> declared
>
> My current task is to map out the clocks within the design hierarchy.
> To do this I identify known clock ports within modules.  For each module
> with a known clock port I find it's parent module and trace the wire
> connected to the clock port to any other sub-modules that use that
> wire.  Once a sub-module that uses that wire is found, I add it's port
> (to which the wire is attached) and add it to:
> $pointer->{$module}{"used_by"}{$parent_module}{$inst_name}{$clk_port} =
> $connected_wire;  (Note: $clk_port has entry does not exist until i do
> the $connected_wire assignment)
>
> The problem is, when I do the assignment, all the instances of all the
> modules end up with a key of $clk_port with a value of $connected_wire.
> All this after one (supposedly single assignment).
>
> Here is the subroutine that idenifies the parent clock and adds the
> clock to it's sub-modules:
> sub add_clock {
>    my ($parent, $sub_mod, $inst, $clk_port, $vnet) = @_;
>    print "Add Clock Data: $parent, $sub_mod, $inst, $clk_port\n";
>    my ($clock) =
> $vnet->{$parent}{"sub_mod"}{$sub_mod}{$inst}{$clk_port};
>    $vnet->{$parent}{"clocks"}{$clock}++;
>    print "Added Parent Clock: $clock to $parent\n";
>    foreach my $sub_mod (keys %{$vnet->{$parent}{"sub_mod"}}) {
>       foreach my $inst (keys %{$vnet->{$parent}{"sub_mod"}{$sub_mod}}) {
>
>          foreach my $port  (keys
> %{$vnet->{$parent}{"sub_mod"}{$sub_mod}{$inst}}) {
>             my ($wire) =
> $vnet->{$parent}{"sub_mod"}{$sub_mod}{$inst}{$port};
>             if ($wire eq $clock) {
>                &print_vnet ($vnet);
>                print qq/Traced Wire: $wire to Inst: $inst Port:
> $port\n/;
>                $vnet->{$sub_mod}{"used_by"}{$parent}{$inst}{$port} =
> $clock;
>                &print_vnet ($vnet);
>                &stop();
>                }
>             }
>          }
>       }
>    }
>
> Here's a sample output from the subroutine  (&print_vnet unwinds
> elements of the data structure, &stop is a break point). Notice the
> first VNET CATALOG with no clock ports identified, then I identify
> CG_CLKOUT1 is connected to CK port of synth_cntl_reg_0A, then notice
> that both of the submodules suddenly have CK identified as clock ports
> connected to CG_CLKOUT1 when only one was assigned.
>
> Add Clock Data: cg_test_1, FL1S3ENV15, synth_cntl_reg_0A, CK
> Added Parent Clock: CG_CLKOUT1 to cg_test_1
>    VNET CATALOG:
>     {FL1S3ENV15}{"clocks"} = CK
>     {cg_test_1}{"sub_mod"}{FL1S3ENV15}{synth_cntl_reg_0A}{CK} =
> CG_CLKOUT1
>     {cg_test_1}{"sub_mod"}{FL1S2EQV15}{pwrdn_cnt_reg_15A}{CK} = xtal_clk
>
>     {cg_test_1}{"clocks"} = CG_CLKOUT1
>     {FL1S2EQV15}{"clocks"} = CK
> Traced Wire: CG_CLKOUT1 to Inst: synth_cntl_reg_0A Port: CK
>    VNET CATALOG:
>     {FL1S3ENV15}{"used_by"}{cg_test_1}{synth_cntl_reg_0A}{CK} =
> CG_CLKOUT1
>     {FL1S3ENV15}{"clocks"} = CK
>     {cg_test_1}{"sub_mod"}{FL1S3ENV15}{synth_cntl_reg_0A}{CK} =
> CG_CLKOUT1
>     {cg_test_1}{"sub_mod"}{FL1S2EQV15}{pwrdn_cnt_reg_15A}{CK} = xtal_clk
>
>     {cg_test_1}{"clocks"} = CG_CLKOUT1
>     {FL1S2EQV15}{"used_by"}{cg_test_1}{pwrdn_cnt_reg_15A}{CK} =
> CG_CLKOUT1
>     {FL1S2EQV15}{"clocks"} = CK
>
> And here's the netlist I used: (obviously just for testing)
> module cg_test_1 (CG_CLKOUT1);
> output CG_CLKOUT1;
>     wire xtal_clk;
>     FL1S2EQV15 pwrdn_cnt_reg_15A (.CK(xtal_clk));
>     FL1S3ENV15 synth_cntl_reg_0A (.CK(CG_CLKOUT1));
> endmodule
>
> This one's been bustin' my hump for a while..
>
> Any ideas? If you want to go one on one, I can send you the entire
> script (pretty small).
>
> Thanks.




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