[Hardware-pm] Module::Build::Xilinx 0.01 released

[Vikas N Kumar]

Hi

For those of you who are into learning FPGA development using developer
boards made by Xilinx such as the Spartan-3A Starter Kit, I have
released Module::Build::Xilinx into CPAN right now.

The aim of this module is to enable you to create a custom Tcl makefile 
like program for your VHDL project for the Xilinx dev board, so that you
can actually completely use command line to setup, build, run , simulate
and even program your Xilinx device by running the generated Tcl
makefile with Xilinx's custom Tcl shell.

This module enables you to write a much simpler Build.PL script with
some special parameters that will help auto-generate a complex Tcl file
to make it easier to use Xilinx's ISE WebPack IDE from the commandline.

Currently as of version 0.01 it only supports VHDL and if any Verilog
users are interested I can support that too.

For an example, look in the share/example directory of the source code
or in the share/ directory of the installation to see how to use it with
VHDL source and test files.

Feel free to email me on further details.

Thanks
vicash (vikas at cpan.org)